Vectors & Arrays in Verilog - Part II

2. Arrays- From Vectors to Multidimensional Arrays:

Array:

Two Dimensional Array:

It is very common to Store data in two dimensions. Memories store data in this fashion. One or more bits of data can be stored at one location and the 2-D array may have one or more such data locations.

Loc1	M bits
Loc2	M bits
..	…
.	…
Loc N	M bits

Example: 4x8 array

	00000011
	01010011
	01010011
	01011111

Array declaration:

reg [7:0] rbus [0:3]; //4x8 register array

wire [7:0] wbus [0:3]; //4x8 wire array

Array Access:

assign whole = rbus[0]; //whole is 8 bit wire itself

//answer would be 00000011

Array Bit Select:

assign bit_sel = wbus[0][0]; //0^th bit of byte at 0^th location is assigned to 1 bit wire bit_sel

//answer would be 0

Array part Select:

assign part_sel = wbus[1][2:0]; //0 to 2 bits of wbus’ location 1 are assigned to 3 bit wire part_sel

//answer would be 011

Array usage:

//dut:

module array(
input [7:0] word,
output [7:0] wbyte,
output [2:0] wpart,
output wbit
);
wire [7:0] array_mem [0:3];

assign wbyte = array_mem[0];
assign wbit = array_mem[0][0];
assign wpart = array_mem[1][2:0];

assign array_mem [0] = word;
assign array_mem [1] = word;
assign array_mem [2] = word;
assign array_mem [3] = word;
endmodule

//Test_bench:
module array_tb();
reg [7:0] word;
wire [7:0] wbyte;
wire [2:0] wpart;
wire wbit;
array v1(.word(word), .wbyte(wbyte), .wpart(wpart), .wbit(wbit));
initial begin
word = 8'b0000_1010; #10 word = 8'b0101_0011;
#10 word = 8'b0101_0011; #10 word = 8'b0101_1111; end

initial #45 $finish;
initial $monitor("word=%b \t wbyte=%b \t wpart=%b \t wbit=%b",word,wbyte,wpart,wbit);

endmodule

Simulations Results:

word=00001010 wbyte=00001010 wpart=010 wbit=0

word=01010011 wbyte=01010011 wpart=011 wbit=1

word=01011111 wbyte=01011111 wpart=111 wbit=1