Vectors & Arrays in Verilog - Part I

1. Vectors- From Vectors to Multidimensional Arrays:

VECTORS:

How do you handle arrays in Verilog? Many times over it is required to access arrays in Verilog.

What if you had to store data in a memory as matrix? How will you access the elements of the matrix?

First, let’s have a look at Vectors in Verilog:

Vector: Vector has only one dimension. It is also called a bus notation

Vector declaration:

reg [3:0] rbus; //4 bit wide register vector

wire [3:0] wbus; //4 bit wide wire vector

Vector Access:

assign whole = rbus; //whole is 4 bit wire itself

Vector Bit Select:

assign bit_sel = wbus[0]; //0^th bit of wbus is assigned to 1 bit wire bit_sel

Vector part Select:

assign part_sel = wbus[2:0]; //0 to 2 bits of wbus are assigned to 3 bit wire part_sel

Vector Usage:

//DUT:

module vector_part_sel(

input [3:0] nibble,

output [2:0] wbus,

output wbit

);

assign wbus = nibble[2:0];

assign wbit = nibble[3];

endmodule

//Test_bench:

module vector_part_sel_tb();

reg [3:0] nibble;

wire [2:0] wbus;

wire wbit;

vector_part_sel v1(.nibble(nibble), .wbus(wbus), .wbit(wbit));

initial begin

nibble = 4'b1010; #10 nibble = 4'b0101;

#10 nibble = 4'b1110; #10 nibble = 4'b0111; end

initial #45 $finish;

initial $monitor("nibble=%b \t wbus=%b \t wbit=%b",nibble,wbus,wbit);

endmodule

Simulation Results:

nibble=1010 wbus=010 wbit=1

nibble=0101 wbus=101 wbit=0

nibble=1110 wbus=110 wbit=1

nibble=0111 wbus=111 wbit=0