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Tuesday, 20 December 2011

Aquiring image data from file/memory/port in Verilog - Part II

Acquire image and access:


Let us consider an example where some hardware acquires 8 bits of image data and stores it in the memory. For simplicity, let’s assume that the image is very small say 50 X 37 (that is, there are 50 pixels in a row, let’s call it ‘pixel row’ and there are 37 such ‘pixel rows’ so, 1850 pixels (50 * 37) in total constitute the image). Each pixel is an 8 bit value (ranging from 0 to 255).


With following module and the test bench created by MATLAB in last session 'Aquiring image data from file/memory/port in Verilog - Part I' you can simulate and find out that the image will be stored in hex.

If you need the same photo that I have used then go (copy and paste in browser) to http://www.flickr.com/photos/72479767@N07/6543481245/sizes/t/in/photostream/ and click on 'Download the Thumbnail size of this photo' save as 'poko_50x37.jpg'



module img_mem(clk,out,in,wr
);

parameter col=6'b11_0010; //50
parameter row=6'b10_0101;
parameter data_length=8;

input clk;
//reg [7:0] mem [0:1];
reg [data_length-1:0] mem2 [0:row-1][0:col-1];
output reg [data_length-1:0] out;
input [data_length-1:0] in;
input wr;

//integer i;
reg [5:0] cnt1,cnt2,sizx=row-1,sizy=col-1;



always @ (posedge clk)
begin
if (wr) begin
mem2[cnt1][cnt2] <= in;
if (cnt1 != sizx) begin

if (cnt2 != sizy)
cnt2 <= cnt2 + 1;
else begin
cnt2 <=0; cnt1 <= cnt1 + 1;end
end
else begin
if (cnt2 != sizy)
cnt2 <= cnt2 + 1;
else begin
cnt2<=0; cnt1<=0;
end
end
end
else
out <= mem2[1][1];
end

initial begin

cnt1 <= 0;
cnt2 <= 0;

end

endmodule


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