Aquiring image data from file/memory/port in Verilog - Part I

1. Automated VerilogHDL test-bench generation:

Often, the test-benches need to feed in some unusually large amount of data into the core/DUT. Imagine if you had to write a VerilogHDL test-bench which gets 5000 or more unique data sequences (we will be using this while reading image bytes for an image).

Indeed, creativity it takes to figure out the most efficient and easy way to turn around things. For HDL coding when we talk, it is generating automated and appropriate test-benches.

If one has to read 1850 sequences of input data (like what follows in the session #2) through a test-bench it wouldn’t be wise to hand-code the entire test-bench. Rather, some other languages/way (MATLAB, C etc) may be used to auto-generate the required test-bench file.

If you need the same photo that I have used then go (copy and paste in browser) to http://www.flickr.com/photos/72479767@N07/6543481245/sizes/t/in/photostream/ and click on 'Download the Thumbnail size of this photo' save as 'poko_50x37.jpg'

Take a look at a 60 line MATLAB code that does exactly that. This code generates a .v test-bench file which has approximately 1874 lines:

clc; close all; clear all; moduleNAME='img_mem_tb'; %verilog module name
fileNAME=strcat(moduleNAME,'.v');

Img = imread('poko_50x37.jpg');

YCBCRImg=rgb2ycbcr(Img);

GRAYImg=rgb2gray(YCBCRImg);

figure ,imshow(GRAYImg);

xy = size(GRAYImg);

x=xy(1);

y=xy(2);

delete (fileNAME) %delete older file

delete ('hex.txt')%delete older file

%fid below writes the testbench file for verilog HDL

fid = fopen(fileNAME,, 'a+'); %open to write with append new file

dif = fopen('hex.txt','a+')

fprintf(fid,'module %s;\n',moduleNAME)

fprintf(fid,'parameter data_length=8;\n')

fprintf(fid,'// Inputs\n')

fprintf(fid, 'reg clk;\n')

fprintf(fid, 'reg [data_length-1:0] in;\n')

fprintf(fid, 'reg wr;\n')

fprintf(fid, '// Outputs\n')

fprintf(fid, 'wire [data_length-1:0] out;\n')

fprintf(fid, '// Instantiate the Unit Under Test (UUT)\n')

fprintf(fid, 'img_mem uut (\n')

fprintf(fid, ' .clk(clk), \n')

fprintf(fid, ' .out(out), \n')

fprintf(fid, ' .in(in), \n')

fprintf(fid, ' .wr(wr)\n')

fprintf(fid, ');\n')

fprintf(fid,'always #1 clk=~clk;\n')

fprintf(fid, 'initial begin\n')

fprintf(fid, ' // Initialize Inputs\n')

fprintf(fid, ' clk = 0;\n')

fprintf(fid, ' in = 0;\n')

fprintf(fid, ' wr =1;\n')

for runx=1:1:x

for runy=1:1:y

A=dec2hex(GRAYImg(runx,runy));

fprintf(dif,'%s',A)

fprintf(fid,' #2 in = 8''h ')

fprintf(fid,'%s',A)

fprintf(fid,';');

fprintf(fid,'\n');

end

fprintf(dif,'\n');

end

fprintf(fid, '#2 wr =0;\n')

fprintf(fid, ' end\n')

fprintf(fid, 'endmodule\n')

fclose(fid); % close the verilog testbench file

fclose(dif); % close the hex text file

This embeds the image data in the test-bench as a data (byte) stream just like it would come from a CMOS camera.