VLSI - good if you knew.

Fields in the VLSI:

Field:	Examples:	Domain:	Pre-requisites:
Biomedical	· MRI scans · ECG · Glucose Monitor	DSP, Digital Design	Digital Design/Verilog
Automotive	· Accelerometer to inflate Airbags · Magnetic Suspension · Emission monitor	DSP, Digital Design	Digital Design/Verilog
Computer Vision & Image processing	· Iris recognition · Fingerprint recognition · Gesture recognition · Object tracking and recognition · Compression · Image enhancement	DSP, Digital Design	Digital Design/Verilog
Communication	· Modems · Switches · Routers (intelligent · Switches)	DSP/ Digital Design	Digital Design/Verilog
MEMS	· Accelerometers · Gyro meters · Gas Sensors · Fluid diffusers	Analog/Digital/Physics	Digital Design/Verilog
Computer & peripheral design	· Bus protocols · Processors · Controllers	Digital Design	Digital Design/Verilog

DSP - Digital Signal Processing

MEMS –Micro-Electro-Mechanical-Systems

MRI – magnetic resonance imaging

ECG – Electrocardiography

EDA – Electronic Design Automation

Terms:

VLSI Design Flow – The essential step by step procedure taken for Design, Verification and finally implementation of a VLSI design (Analog or Digital).

Front-end design – Digital Logic Design.

Back-end design – Physical (transistor level) Implementation of the Front-end.

Digital VLSI Design – Uses Verilog to describe the design or the system. ICs designed in this flow is also called Semi-Custom ICs

Analog VLSI Design – Uses Schematic capture to describe the design or the system. The chip produced in this way are also called Custom-ICs.

Verification – Both Digital and Analog Design have Verification phase but differ.

ASIC – Application Specific Integrated Circuits (functionality can not be changed), both Digital and Analog Designs can be implemented with an ASIC flow. If the design performance is important.

FPGA – Field Programmable Gate arrays (functionality can be changed upon programming, FPGAs are re-programmable), currently not for Analog design, only digital designs. If time-to-market is important.

Physical Design for ASIC – Creating Layout of an ASIC design. This layout contains geometric representation of transistors and their connectivity. The layout is sent to fabrication facility.

Fabrication – ASIC Layout is sent to the foundry or a fabrication facility (company) to finally implement on silicon.

EDA tools – Extremely sophisticated state-of-the-art and highly accurate Software(s) needed to carry out a VLSI design flow. Some companies creating selling these tools are, Cadence, Synopsys, Mentor Graphics, Agnisys, Carbon (search for more on google).

Skill Sets required for Core electronics companies:

Front-end Design: Verilog HDL, tcl-tk, Linux, C, Digital design fundamentals, good logic sense, CMOS fundamentals and basic electronics concepts.

Front-end Verification: SystemVerilog, Verilog, tcl-tk, Linux, C, Digital design fundamentals, good logic sense, CMOS fundamentals and basic electronics concepts.

Capabilities industry looks for:

Quick Learner, team player, good attitude and aptitude, determination and initiative.

Important Links:

FPGA: http://www.fpga4fun.com/ , http://www.asic-world.com/ ,

MEMS: https://www.mems-exchange.org/MEMS/what-is.html

How to choose a field?

Find out what you like doing in the electronics, the most. If you like to design micro chips, you would go for VLSI design.

If you like small controlling applications, go for embedded. And so on.

In VLSI, how to choose a domain?

If you like to design image processing hardware then you would definitely choose Signal processing as your domain. If you want to design chip that would fit in a router or want to design a Bluetooth chip you would go for communication.

Parameterized Modules and Function

Parametrized modules and function: goes a long way

Often functions are very important and using them will make parametrized generic code creation in HDL trivial. If you had ever wondered how to find the number of bits required to hold a count in a parametrized generic counter then this tutorial will be a nice read and resource for you.

Consider a scenario where you have designed a rigid counter that counts from 0 to 31 that is, mod 32 counter. For this counter 5 bits are enough to hold the count from 0 to 31 (number of bits=log2(count)).

You would write the code something like this:

//counter with synchronous reset:

module counter(

clk,

rst,

count

);

input clk,rst;

output [4:0] count; //now 4:0 is 5 bits to hold 32 counts //<-------change here
reg [4:0] count; //<-------change here

always @( posedge clk)

begin

if (rst)

count<=0;

else begin

if (count<31) //<-------change here

count<=count+1;

else

count<=0;

end

endmodule

//counter test bench:
module counter_tb();

reg clk,rst;
wire [31:0] count; //<----------change here

counter cnt1(.clk(clk),
.rst(rst),
.count(count)
);

always #1 clk=~clk;

initial begin

clk=0; rst=0;

#2 rst=1;

#2 rst=0;
end

endmodule

Fair enough! What if you need a counter that can count to 100 and yet, later, after some days you want a counter that can count to 1000? This goes on and you will have to change each place where you have those constant values in the above example every time over and over again. In this particular example you will have to change at four places in the code (including the testbench) and will have to calculate the number of bits that can hold the count using a calculator.

To start with, it would have been better if you had thought to design a parametrized generic counter instead.

How would you do that? You need to make a function to find the log and use variables at the placed where constant are required. Let us see this with help of an example.

First of all create a function in a text file as given here and save the file as maths.fn:

function integer logb2;

input [31:0] Depth;

integer i;

begin

i = Depth;

for(logb2 = 0; i > 0; logb2 = logb2 + 1)

i = i >> 1;

end

endfunction

Now you have a text file maths.fn that contains the function that we are going to use

Let's create the parametrized counter module and its testbench as given here:

Try to look at it and understand:
module counter_parameterized(

clk,

rst,

count

);

//Note this change:

`include " maths.fn"

Parameter count_max = 32;

parameter count_width= logb2 (count_max);

input clk,rst;

output [count_width-1:0] count; //variable
reg [count_width-1:0] count;

always @( posedge clk)

begin

if (rst)

count<=0;

else begin

if (count< count_max-1)

count<=count+1;

else

count<=0;

end

endmodule

Now, look at its testbench as well:

//counter test bench:
module counter__parameterized _tb();

parameter val=32 // <------change just here!!

reg clk,rst;
wire [val-1:0] count;

counter_parameterized #(
. count_max(val)
)
cnt1(.clk(clk),
.rst(rst),
.count(count)
);

always #1 clk=~clk;

initial begin

clk=0; rst=0;

#2 rst=1;

#2 rst=0;
end

endmodule

See? This way you have to change the code at just one place and that is, where the code has been instantiated ONLY!! Moreover, the effort of finding out the number of bits required for the counter has been saved. This little effort goes a long way in the long run and saves lots of effort as the code gets bigger.

NB. Make sure that the math.fn file that you created is in the root directory of the project you are working in and is added to the project.

Aquiring image data from file/memory/port in Verilog - Part II

Acquire image and access:

Let us consider an example where some hardware acquires 8 bits of image data and stores it in the memory. For simplicity, let’s assume that the image is very small say 50 X 37 (that is, there are 50 pixels in a row, let’s call it ‘pixel row’ and there are 37 such ‘pixel rows’ so, 1850 pixels (50 * 37) in total constitute the image). Each pixel is an 8 bit value (ranging from 0 to 255).

With following module and the test bench created by MATLAB in last session 'Aquiring image data from file/memory/port in Verilog - Part I' you can simulate and find out that the image will be stored in hex.

If you need the same photo that I have used then go (copy and paste in browser) to http://www.flickr.com/photos/72479767@N07/6543481245/sizes/t/in/photostream/ and click on 'Download the Thumbnail size of this photo' save as 'poko_50x37.jpg'

module img_mem(clk,out,in,wr
);

parameter col=6'b11_0010; //50
parameter row=6'b10_0101;
parameter data_length=8;

input clk;
//reg [7:0] mem [0:1];
reg [data_length-1:0] mem2 [0:row-1][0:col-1];
output reg [data_length-1:0] out;
input [data_length-1:0] in;
input wr;

//integer i;
reg [5:0] cnt1,cnt2,sizx=row-1,sizy=col-1;



always @ (posedge clk)
begin
if (wr) begin
mem2[cnt1][cnt2] <= in;
if (cnt1 != sizx) begin

if (cnt2 != sizy)
cnt2 <= cnt2 + 1;
else begin
cnt2 <=0; cnt1 <= cnt1 + 1;end
end
else begin
if (cnt2 != sizy)
cnt2 <= cnt2 + 1;
else begin
cnt2<=0; cnt1<=0;
end
end
end
else
out <= mem2[1][1];
end

initial begin

cnt1 <= 0;
cnt2 <= 0;

end

endmodule